Heretofore, fail-safe on-delay circuits using a resistor and four terminal capacitor, as disclosed for example in U.S. Pat. No. 4,667,184 by Futsuhara, have been used for contactless type on-delay circuits employing conventional electronic circuits.
As shown in FIG. 1, such an on-delay circuit 1, comprises a resistor R1, a four terminal capacitor C1, and a two input window comparator WC which generates an output of logic value 1 when a signal of a level higher than a power source voltage is input to both input terminals A and B.
With this circuit, the input resistance of the window comparator is made sufficiently high compared to that of the resistor R1, so that when an input signal of y=1 (an input signal of a level higher than the power source potential Vcc) is input to a signal input terminal Uy of the on-delay circuit 1, the four terminal capacitor C1 is charged, and the charged voltage is applied to both input terminals A and B of the window comparator WC. When the signal level of the input to the input terminals A and B exceeds a threshold value pre-set for the window comparator WC and which is higher than the power source potential Vcc, the window comparator WC generates an output, and an output signal z=1 of logic value 1 is generated as the output of the on-delay circuit 1. Accordingly, with the on-delay circuit 1, the oscillation delay, that is the delay time of the on-delay circuit 1, is determined by the resistor R1, the four terminal capacitor C1 and the threshold value of the window comparator WC.
Another type of on-delay circuit using a UJT (uni-junction transistor) is proposed by Futsuhara in Japanese Examined Patent Publication No. 1-3006, and in The Transaction of The Institute of Electrical Engineers of Japan Vol. 104-C, No.2 (February 1984) PP. 1.about.6.
With these on-delay circuits, the former on-delay circuit has a fail-safe construction, since in the event of a disconnection fault in the resistor, or a disconnection or short circuit fault in the terminals of the four terminal capacitor, an output is not generated. However, the time delay cannot be set very long. If a long time delay is required, then there is no other way but to use mechanical type timers such as a motor timer wherein the rotation of a motor is reduced in speed through a speed reducer to operate contact points.
With the latter on-delay circuit using a UJT, this has disadvantages such as; (1) erroneous signal generation due to a short circuit fault between the terminals of the UJT itself is not covered, and (2) since there is no threshold value operation function provided in the circuit which stores the delay pulse signal, the abovementioned erroneous signal generation cannot be dealt with.
The present invention takes into consideration the abovementioned situation with the object of providing a practical on-delay circuit using a fail-safe electronic circuit, which covers all possible failure modes.